1. Field of the Invention
The present invention relates to a circuit for driving a plasma display panel (PDP). More specifically, the present invention relates to a circuit for driving a PDP that is capable of preventing a scan driving integrated circuit (IC) from being damaged.
2. Description of the Related Art
In general, a PDP is a next generation flat plate display for displaying characters or images using plasma generated by gas discharge. Pixels ranging from hundreds of thousands to more than millions are arranged in the form of a matrix according to the size of the PDP.
PDPs are divided into direct current (DC) PDPs and alternating current (AC) PDPs according to the shape of the waveform of an applied driving voltage and the structure of a discharge cell. Current directly flows in discharge spaces while a voltage is applied in the DC PDP, because electrodes are exposed to the discharge spaces. Therefore, a resistor for restricting the current must be used outside of the DC PDP. On the other hand, in the case of the AC PDP, the current is restricted due to the natural formation of capacity because a dielectric layer covers the electrodes. The AC PDP has a longer life than the DC PDP because the electrodes are protected against the shock caused by ions during discharge.
A memory characteristic that is one of the important characteristics of the AC PDP is caused by the capacity due to the dielectric layer that covers the electrodes.
According to the light emission principle of the AC PDP, discharge occurs because an electric potential difference in the form of a pulse is formed in scan electrodes and sustain electrodes. At this time, vacuum ultraviolet (UV) rays generated in a discharge process are excited to red (R), green (G), and blue (B) fluorescent bodies. The respective fluorescent bodies emit light due to light combination.
The discharge is affected by various parameters such as the kind and the pressure of the discharge gas inside the PDP, the secondary electron emission characteristic of an MgO protecting film, and the structures and the driving conditions of the electrodes.
An address and display separate (DS) driving method of the PDP includes a reset period, an address period, and a sustain period. In the reset period, the charge state of each cell is initialized so that an addressing operation can be smoothly performed on the cell. In the address period, cells that are turned on and cells that are not turned on are selected among the cells initialized by a reset operation, address discharge occurs only in the cells that are turned on, and wall charge is accumulated in the sustain electrodes.
In the sustain period, sustain discharge is performed by the sum of a voltage caused by the wall charge accumulated in the address period and a sustain discharge pulse alternately applied to both the scan electrodes and the sustain electrodes in order to actually display a picture on addressed cells.
An apparatus for driving a common PDP includes a controller, an address driving IC, a scan driving IC, and a sustain driving IC.
FIG. 1 is a block diagram showing a structure of the scan driving IC of the common PDP in accordance with the prior art.
As shown in FIG. 1, the scan driving IC 10 includes two field-effect transistors and a plurality of circuits having outputs positioned between the two field-effect transistors. Therefore, the scan driving IC 10 has a plurality of multiple outputs Y1, Y2, Y3, . . . Yn−1, and Yn. The multiple outputs are respectively connected to the panel capacitance Cp, that is, Cp1,Cp2, Cp3, . . . Cpn−1, and Cpn.
The AC PDP has a capacitive panel load. The panel capacitance Cp precedes charge and discharge operations during the driving of the PDP.
Between both ends of the scan driving IC 10, Vout—L applies a waveform loaded with main data to a panel, and power recovered through a power recovery circuit of the panel is applied to Vout—H. In addition, Vout—H sustains the same level as the electric potential of Vout—L through internal diodes of the field-effect transistors inside the scan driving IC 10. Therefore, it is difficult to damage the scan driving IC 10 during the normal operation of the PDP.
When a scan voltage is applied to the PDP, because a voltage loaded in the scan driving IC 10 is applied as the stress of the IC, the scan voltage is determined by the rated voltage of the scan driving IC 10.
In a case where the PDP abnormally operates, or if switches (not shown) connected to the rear port of the scan driving IC 10 fail to operate properly, when the Vout—H potential of the scan driving IC 10 is applied to be higher than the Vout—L potential by a degree of no less than the rated voltage of the scan driving IC 10, the scan driving IC 10 is damaged. Actually, during experiments or running operations, the scan driving IC 10 is found to be often damaged.
When the rated voltage of the scan driving IC 10 is between about 100 and 150V, the maximum operation voltage of the PDP is between 400 and 500V, so the PDP normally operates and Vout—H and Vout—L sustain the same level.
However, when a switch arranged between Vout—L and Vout—H fails to operate properly in a state where a voltage of 450V is loaded in to Vout—L and Vout—H, Vout—H is sustained to be at 450V. Because Vout—L is connected to a ground, an electric potential difference between Vout—H and Vout—L is approximately 450V. Therefore, because the electric potential difference between both ends of the scan driving IC 10 is 450V, which is higher than the rated voltage of the scan driving IC 10 of between 100 and 150V, the scan driving IC is damaged.
Because the scan driving IC 10 is expensive and not easily repaired, this results in a cost-prohibitive repair.